著作(Publication)

Journal Papers:          Conference Papers   Books

1.       Trong-Yen Lee, Min-Jea Liu, Chia-Han Huang, Chia-Chen Fan, Chia-Chun Tsai, and Haixia Wu, “Design of a Digit-Serial Multiplier Over GF(2^m) Using a Karatsuba Algorithm,” Journal of the Chinese Institute of Engineers, doi:10.1080/02533839.2019.1644200. Aug. 2019.

2.       Chia-Chun Tsai, “Performance Evaluation for Stacked-Layer Data Bus Based on Isolated Unit-size Repeater Insertion,” Advances in Technology Innovation, Vol. 4, No. 3, pp. 197-209, July 2019.

3.       Chia-Chun Tsai, “Data Access Time Reduction for 3D Data Bus in Mixed Cases of Embedded Bus Switches and Inserted Signal Repeaters,” International Journal of Electronics Communication and Computer Engineering, Vol. 10, No. 3, pp. 127-140, May 2019.

4.       Chia-Chun Tsai, “An Effective Algorithm for Minimizing the Critical Access Time of a 3D-Chip Data Bus,” International Journal of Electronics Communication and Computer Engineering, Vol. 9, No. 4, pp. 117-123, July 2018.

5.       Chia-Chun Tsai, “2.5D X-Clock Tree Synthesis Based on Voltage-Island Combination for Reducing Power and Delay,” International Journal of Engineering Research & Sciences, Vol. 3, No. 2, pp. 14-23, Feb. 2017.

6.       Shin-Chi Lai, Wen-Ho Juang, Yi-Hsiang Juan, Ching-Hsing Luo, and Chia-Chun Tsai, “A Low-Complexity Recursive Algorithm and Compact Hardware Design for Sliding Discrete Fourier Transform," International Journal of Electrical Engineering, Vol. 23, No. 2, pp. 73-81, April 2016.

7.       Shin-Chi Lai, Wei-Jhe Ma, Wen-Ho Juang, Kuan-Ying Chang, Wen-Chih Li, Te-Hsuan Hung, Siang-Ling Lu, Pei-Chen Tai, Ching-Hsing Luo, Chia-Chun Tsai, and Chiung-Hon Lee, “Thumb-based ECG Signal Acquisition System with Digital Signal Processing Algorithms," International Journal of Electrical Engineering, Vol. 23, No. 2, pp. 83-93, April 2016.

8.       Shin-Chi Lai, Wen-Ho Juang, Yueh-Shu Lee, Shin-Hao Chen, Ke-Horng Chen, Chia-Chun Tsai and Chiung-Hon Lee, ”Hybrid Architecture Design for Calculating Variable-Length Fourier Transform,” IEEE Trans. On Circuits and Systems II, Vol. 63, No. 3, pp. 279-283, Mar. 2016.

9.       Chia-Chun Tsai, “Power Aware Based on Voltage Islands for X-Clock Tree Construction,” International Journal of Engineering and Applied Sciences, Vol. 2, No. 11, pp. 11-18, Nov. 2015.

10.    Miao-Sheng Chen, Wu-Lung Huang, Kuang-Min Wu, and Chia-Chun Tsai, “Qnew-Video Course Consultative System,” Advanced Materials Research, Vols. 655-657, pp. 1839-1942, Jan. 2013.

11.    Kuan-Yu Lin, Hong-Ting  Lin, Tsung-Yi Ho, and Chia-Chun Tsai, “Load-Balanced Clock Tree Synthesis with Adjustable Delay Buffer Insertion for Clock Skew Reduction in Multiple Dynamic Supply Voltage Designs,” ACM Trans. on Design Automation of Electronic Systems, Vol. 17, No. 3, Article 34, June 2012.

12.    Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, and Trong-Yen Lee, “Discharge-Path-Based Antenna Effect Detection and Fixing for X-Architecture Clock Tree,” Integration, the VLSI Journal, Vol. 45, No. 1, pp. 76-90, Jan. 2012.

13.    Chia-Chun Tsai, Chung-Chieh Kuo, and Trong-Yen Lee “High Performance Buffered X-Architecture Zero-Skew Clock Tree Construction with Via Delay Consideration,” International Journal of Innovative Computing, Information and Control, Vol. 7, No. 9, pp. 5145-5161, Sept. 2011.

14.    Chia-Chun Tsai, Sheng-Bin Dai, and Trong-Yen Lee, “The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B,” Journal of Circuits, Systems, and Computers, Vol. 20, No. 8, pp. 1637-1658, Aug. 2011.

15.    Trong-Yen Lee, Che-Cheng Hu, Yang-Kun Huang, and Chia-Chun Tsai, “Adaptive Frame Length Method for Hardware Context-switching in Dynamic Partial Self-reconfigurable Systems,” International Journal of Innovative Computing, Information and Control, Vol. 7, No. 3, pp. 1427-1442, Mar. 2011.

16.    Chia-Chun Tsai, Chung-Chieh Kuo, and Trong-Yen Lee “Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E94-A   No.2   pp. 706-716, Feb. 2011.

17.    Chung-Chieh Kuo, Chia-Chun Tsai, and Trong-Yen Lee, “Pattern-matching-based X-Architecture Zero-skew Clock Tree Construction with X-Flip Technique and Via Delay Consideration,” Integration, the VLSI Journal, Vol. 44, No. 1, pp. 87-101, Jan. 2011.

18.    Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, and Chia-Chun Tsai, “Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems,” Journal of Information Science and Engineering, Vol. 26, No. 4, pp. 1289-1305, July 2010.

19.    Chia-Chun Tsai, Chung-Chieh Kuo, and Trong-Yen Lee, “Jumper Insertion for Antenna Avoidance in X-clock Routing,” Far East Journal of Electronics and Communications, Vol. 4, No. 2, pp. 123-132, June 2010.

20.    Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, and Chia-Chun Tsai, “Hardware-software Partitioning for Embedded Multiprocessor FPGA Systems,” International Journal of Innovative Computing, Information and Control, Vol. 5, No. 10, pp. 3071-3083, Oct. 2009.

21.    Chia-Chun Tsai, Jan-Ou Wu, and Trong-Yen Lee, “Maximal Delay Reduction for RLC-Based Multi-source Multi-sink Bus with Repeater Insertion,” Circuits, Systems & Signal Processing, Vol. 28, No. 6, pp. 805-817, Aug. 2009.

22.    Chia-Chun Tsai, Chin-Yen Lin, Yuh-Shyan Hwang, and Trong-Yen Lee, “The Design of a Li-Ion Battery Charger Based on Multimode LDO Technology,” Journal of Circuits, Systems, and Computers, Vol. 18, No. 5, pp. 947-963, Aug. 2009.

23.    Chia-Chun Tsai, Kai-Wei Hong, and Trong-Yen Lee, “A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital Converters,” Journal of Circuits, Systems, and Computers, Vol. 18, No. 5, pp. 933-945, Aug. 2009.

24.    Chia-Chun Tsai, Huang-Chi Chou, and Trong-Yen Lee, “The Circuit Design of Current-Mode Image Sensor Embedded Smooth Spatial Filter with Flash A/D Converter,” WSEAS Transactions on Circuits and Systems, Issue 2, Vol. 8, pp. 237-246, Feb. 2009.

25.    Trong-Yen Lee, Yang-Hsin Fan, and Chia-Chun Tsai, “Adaptive Multi-Constraints in Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems,” WSEAS Transactions on Computers, Issue 2, Vol. 8, pp. 334-343, Feb. 2009.

26.    Chia-Chun Tsai, Jan-Ou Wu, and Trong-Yen Lee, “GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E91-A, No.1, pp. 365-374, Jan. 2008.

27.    Chia-Chun Tsai, Jan-ou Wu, Chien-Wen Kao, and Trong-Yen Lee, “Coupling-Aware RLC-Based Clock Routing for Crosstalk Minimization,” WSEAS Transactions on Circuits and Systems, Vol. 6, Issue 9, pp. 559-565, Sep. 2007.

28.    Chia-Chun Tsai, Kwok-Fong Kual, and Trong-Yen Lee, “An RF Circuit Design of Transmission Interface for ISO14443A RFID Transponders,” WSEAS Transactions on Circuits and Systems, Vol. 6, Issue 8, pp. 532-538, Aug. 2007.

29.    Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, and Trong-Yen Lee, “Zero-Skew Driven for Buffered RLC Clock Tree Construction,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E90-A, No. 3, pp. 651-658, March 2007.

30.    Yuh-Shyan Hwang, Jiann-Jong Chen, Sing-Yen Wu, Lu-Po Liao, and Chia-Chun Tsai, ”A New Pipelined Analog-to-Digital Converter Using Current Conveyors,” Analog Integrated Circuits and Signal Processing, Vol. 50, No. 3, pp. 213-220, Mar. 2007.

31.    Jan-Ou Wu, Chia-Chun Tsai, Yu-Ting Hsieh, and Trong-Yen Lee, “Grey Relational Clustering Associated with DME Algorithm for Zero-Skew Clock Tree Construction in SoC,” The Journal of Grey System, Vol. 18, No. 4, pp. 287-304, Dec. 2006.

32.    Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, and Jan-Ou Wu, “Using Stack Reconstruction on RTL Orthogonal Scan Chain Design,” Journal of Information Science and Engineering, Vol. 22, No. 6, pp. 1585-1599, Nov. 2006, Taiwan.

33.    Chia-Chun Tsai, Hsu-Heng Wu, Wen-Ta Lee, Jan-Ou Wu and Trong-Yen Lee, “A Fractional Frequency Synthesizer Based on ADPLL,” International Journal of Electrical Engineering, Vol. 12, No. 4, pp. 325-332, Nov. 2005.

34.    Chia-Chun Tsai, Po-Kuan Tien, Wen-Ta Lee, Jan-Ou Wu and Trong-Yen Lee, “Power and Data Transfer Techniques Applied for RFID Systems,” International Journal of Electrical Engineering, Vol. 12, No. 3, pp. 261-267, Aug. 2005.

35.    Chia-Chun Tsai, Chien-Hung Lai, Wen-Ta Lee, and Jan-Ou Wu, “A 10-Bit Switched-Current Digital to Analog Converter,” IEE Proceedings – Circuits, Devices and Systems, Vol. 152, Issue 3, pp. 287-290, June 2005.

36.    Jan-Ou Wu, Chia-Chun Tsai, Wen-Ta Lee, and Trong-Yen Lee, “Cell Compaction with Jogs Insertion Based on 45°-Shear Line,” Journal of Technology, Vol. 20, No. 1, pp. 83-90, March 2005.

37.    Pei-Yung Hsiao, Yu-Chun Hsu, Wen-Ta Lee, Chia-Chun Tsai, and Chia-Hao Lee, “An Embedded Analog Spatial Filter Design of The Current-Mode CMOS Image Sensor,” IEEE Transactions on Consumer Electronics, Vol. 50, No. 3, Aug. 2004, pp. 945-951.

38.    Jan-Ou Wu, Chyun-Shin Cheng, and Chia-Chun Tsai, “Application of Grey Relational Analysis to Minimal Clock Skew Routing in SoC,” The Journal of Grey System, vol. 16, no.3, Aug. 2004, pp. 221-234.

39.    Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, and Wen-Ta Lee, “RLC Exact Zero-Skew Algorithm,” Journal of National Taipei University of Technology, Vol. 37-1, March 2004, pp. 223-232.  

40.    Chia-Chun Tsai, Jan-Ou Wu, Ming-Chong Lee, and Wen-Ta Lee, “Prediction-Based Ahead on Simulated Annealing for Array Placement,” Journal of National Taipei University of Technology, Vol. 37-1, March 2004, pp. 215-222.  

41.    Trong-Yen Lee, I-Mu Wu, Chien-Pin Chang, Pao-Ann Hsiung, Chia-Chun Tsai, and Wen-Ta Lee, “Design of a Software Synthesis Tool for Real-Time Embedded System,” Journal of National Taipei University of Technology, Vol. 37-1, March 2004, pp. 179-196.  

42.    Wen-Ta Lee, Jian-Liang Ye, and Chia-Chun Tsai, “Design and Implementation of a Portable MP3 Player,” Journal of National Taipei University of Technology, Vol. 37-1, March 2004, pp. 159-167.  

43.    Wen-Ta Lee, Chien-Fang Pang, Chia-Chun Tsai, and Trong-Yen Lee, “A Window-based Reconfigurable Punctured Convolutional Encoder/Decoder IP Builder,” Journal of National Taipei University of Technology, Vol. 37-1, March 2004, pp. 149-158.  

44.    Wen-Sheng Chiang, Wen-Ta Lee, and Chia-Chun Tsai, “Chip Implementation for Improved Booth Multiplier,” Journal of National Taipei University of Technology, Vol. 35-1, March 2002, pp. 141-147.  

45.    Ping-Hong Liu, Wen-Ta Lee, and Chia-Chun Tsai, “Chip Design of Low Power Motion Detection Processor,” Journal of National Taipei University of Technology, Vol. 35-1, March 2002, pp. 131-139.  

46.    Jan-Ou Wu, Chia-Chun Tsai, and Wen-Ta Lee, “Edged Shear Line Techniques Applied to Cell Compaction,” Journal of National Taipei University of Technology, Vol. 35-1, March 2002, pp. 103-113.  

47.    Jan-Ou Wu, Chyun-Shin Cheng, and Chia-Chun Tsai, “The Application of Grey Multi-Objective Decision Making In Data Structure of VLSI Layout Selection,” Journal of National Taipei University of Technology, Vol. 34-1, March 2001, pp. 99-107.  

48.    Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, and Chia-Chun Tsai, “Efficient Routability Check Algorithms for Segmented Channel Routing,” ACM Trans. on Design Automation of Electronic Systems. Vol. 5, No. 3, July 2000, pp. 735-747.

49.    Shuenn-Shi Chen, Jong-Jang Chen, Chia-Chun Tsai, and Sao-Jie Chen, “An Automatic Router for the Pin Grid Array Package,” IEE Proceedings, Computers and Digital Techniques, vol. 146, no. 6, Nov. 1999, pp. 275-282.

50.    Shuenn-Shi Chen, Jong-Jang Chen, Trong-Yen Lee, Chia-Chun Tsai, and Sao-Jie Chen, “A New Approach to the Ball Grid Array Package Routing,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E82-A, no. 11, Nov. 1999, pp. 2599-2608.

51.    Chia-Chun Tsai, "Minimal Crosstalk River Routing,” Journal of National Taipei University of Technology, Vol. 32-1, March 1999, pp. 175-193.

52.    Ji-Pong Fang and Chia-Chun Tsai, "One Dimensional Compactor Implementation,” Journal of National Taipei University of Technology, Vol. 31-2, Sep. 1998, pp. 43-55.  

53.    Chia-Chun Tsai, "Timing Driven Based on Signal Repeater Insertion,” Journal of National Taipei University of Technology, Vol. 31-2, Sep. 1998, pp. 111-133.

54.    Chia-Chun Tsai, "Routing Around a Rectilinear Module,” Journal of The Chinese Institute of Electrical Engineering, Vol. 5. No. 1, Feb. 1998, pp. 1-12.

55.    Chia-Chun Tsai, Chwan-Ming Wang, and Sao-Jie Chen, "NEWS: A Net Evenly Wiring System for the Routing on a Multi-Layer PGA Package,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 2, Feb., 1998, pp. 182-189.

56.    Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, and Sao-Jie Chen, “Hmap: A Fast Mapper for EPGAs Using Extended GBDD Hash Tables,” ACM Trans. on Design Automation of Electronic Systems, Vol. 2, No. 2, April 1997, USA, pp. 135-150.

57.    Chia-Chun Tsai, De-Yu Kao, and Chung-Kuan Cheng, "Performance Driven Bus Buffer Insertion,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 4, April 1996, USA, pp. 429-437.

58.    Chia-Chun Tsai, and Sao-Jie Chen, "Planar Routing in a Pin Grid Array Package,” Journal of The Chinese Institute of Electrical Engineering, Vol. 3, No. 1, pp. 1-12, Feb. 1996, Taiwan.

59.    Sao-Jie Chen, Chia-Chun Tsai, Yuh-Lin Chen, and Yu-Hen Hu, "General Area Router Based on Planning Techniques,” IEE Proceedings-E Computers and Digital Techniques, Vol. 141, No. 6, Nov. 1994, UK, pp. 413-420.

60.    Sao-Jie Chen, Yuh-Lin Chen, Chia-Chun Tsai, and Yu-Hen Hu, "GEAR: A General Area Router,” Journal of the Chinese Institute of Electrical Engineering, Vol. 1, No. 2, pp. 131-143, 1994, Taiwan.

61.    Chia-Chun Tsai, "An Algorithm For Routing Ring Area,” Journal of Taipei Institute of Technology, Vol. 27-1, pp. 313-330, May 1994, Taiwan.

62.    Chia-Chun Tsai and Sao-Jie Chen, "A Linear Time Algorithm for Planar Moat Routing,” Journal of Information Science and Engineering, Vol. 10, No. 1, pp. 111-127, March 1994, Taiwan.

63.    Chia-Chun Tsai, Sao-Jie Chen, and Wu-Shiung Feng, "An H-V Alternating Router,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No. 8, August 1992, USA, pp. 976-991.

64.    Chia-Chun Tsai, "Planar Routing on Moat Area,” Journal of Taipei Institute of Technology, Vol. 25-2, June 1992, Taiwan, pp. 119-136.

65.    Chia-Chun Tsai, Sao-Jie Chen, Pei-Yung Hsaio, and Wu-Shiung Feng, "Routing Area Compaction Based on Iterative Construction,” Journal of The Chinese Institute of Engineer (JCIE), May 1991, Taiwan, pp. 239-256.

66.    Pei-Yung Hsiao, S. F. Chen, Chia-Chun Tsai, and Wu-Shiung Feng, "A Knowledge-Based Program For Compacting Mask Layout of Integrated Circuits,” Computer-Aided Design (CAD), April 1991, UK, pp. 223-231.

67.    Chia-Chun Tsai, "A Heuristic Algorithm of Multilayer Net Connection for VLSI and PCB Design,” Journal of Taipei Institute of Technology, Vol. 24, March 1991, Taiwan, pp. 557-592.

68.    Pei-Yung Hsiao, and Chia-Chun Tsai, "Expert Compactor: A Knowledge-Based Application in VLSI Layout Compaction,” IEE Proceedings-E Computers and Digital Techniques, Vol. 138. No. 1, Jan. 1991, UK, pp. 13-20.

69.    Chia-Chun Tsai, Sao-Jie Chen, Pei-Yung Hsiao, and Wu-Shiung Feng, "A New Iterative Construction Approach to Routing With Compacted Area,” IEE Proceedings-E Computers and Digital Techniques, Vol. 138. No. 1, Jan. 1991, UK, pp. 57-71.

70.    Chia-Chun Tsai, Sao-Jie Chen, and Wu-Shiung Feng, "Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme,” Computer-Aided Design (CAD), September 1990, UK, pp. 423-433.

71.    Chia-Chun Tsai, Sao-Jie Chen, and Wu-Shiung Feng, "An H-V Tile-Expansion Router,” Journal of Information Science and Engineering (JISE), Vol. 6, No. 3, September 1990, Taiwan, pp. 173-189.

72.    Chia-Chun Tsai, “Vertical and Horizontal Channel Expansion Router,” Journal of Nan-Kang Vocational High School, Vol. 7, pp. 239-268, May 1989.  

73.    Chia-Chun Tsai, “Normal Distribution Research and PASCAL Programming Analysis,” Journal of Nan-Kang Vocational High School, Vol. 4, pp. 203-265, May 1984.  

Conference Papers:

1.     Chia-Chun Tsai, “Performance Improvement for Stacked-Layer Data Bus Reconstruction on Complete Timing Period,” The 16^th International SoC Design Conference (ISOCC), paper ID:25, Oct. 6-9, 2019, Jeju, Korea.

2.     Chia-Chun Tsai, “Evaluation for Stacked-Layer Data Bus Based on Isolated Unit-size Repeater Insertion,” International Conference on Advanced Technology Innovation (ICATI), Paper ID: CF9018, July 15-18, 2019, Sapporo, Japan.

3.     Chia-Chun Tsai, Shin-Shen Ho, and Wei-Jhih Chen, “Smart Helmet Design and Implementation,” The 16th Conference on Microelectronics Technology and Applications, Paper ID:E18, pp. 329-334, May 25, 2018, Kaohsiung, Taiwan.

4.     Chia-Chun Tsai and Jhavik Gaudemar Bfern KIGNOUMBA, “World Clock Design and Implementation,” The 2^nd Sustainable Development & Green Technology Symposium, Paper ID:42, April 14, 2018, Chiayi, Taiwan.

5.     Chia-Chun Tsai, “Embedded Bus Switches on 3D Data Bus for Critical Access Time Reduction,” The 9^th IEEE Latin American Symposium on Circuits and Systems (LASCAS), Paper ID-16, Feb 25-28, 2018, Puerto Vallarta, Mexico.

6.     Chia-Chun Tsai, “Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and Repeaters,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 140-145, July 3-5, 2017, Bochum, Germany.

7.     Chia-Chun Tsai, Yu-Chen Dai, and Kai-Jun Chang, “Personal Computer Defense System,” The 15th Conference on Microelectronics Technology and Applications, Paper ID:E13, pp. 435-440, May 19, 2017, Kaohsiung, Taiwan.

8.     Chia-Chun Tsai, Yu-Yi Chen, and Jian-Yu Su, “An Intelligent System for Monitoring Level Crossing,” The 1^st Sustainable Development & Green Technology Symposium, Paper ID:1B11, April 8, 2017, Chiayi, Taiwan.

9.     Chia-Chun Tsai, “A Heuristic Algorithm for Critical Access Time Minimization on 3D Data Bus,” The 27th VLSI Design/CAD Symposium, Paper ID:182, Aug. 2-5, 2016, 85 Sky Tower Hotel, Kaohsiung, Taiwan.

10.  Chia-Chun Tsai, “2.5D X-Clock Tree Construction Based on Stacked-Layer Combination of Multivoltage Islands,” IEEE The Third International Symposium on Computer, Consumer and Control (ISC3),  pp. 443-446, July 4-6, 2016, Xi’an, Mainland China.

11.  Chia-Chun Tsai, Yu-Bo Lai, and Jun-Yi Wu, “An Intelligent System for Monitoring Heartbeat Pulse,” The 11th International Symposium on Healthcare Information Management, Paper-K1, April 23-24, 2016, Tainan, Taiwan.

12.  Chia-Chun Tsai, Yan Jun-Xiang, Dong-Yen Lee, and Xie Cong-Rong, “An Intelligent Waterslide Monitoring System,” The 11th International Symposium on Healthcare Information Management, Paper-C2, April 23-24, 2016, Tainan, Taiwan.

13.  Chun-Chun Tsai, Cheng-En Lee, Ming-Feng Ho, and Kok-Swee Sim, “An Intelligent System for Monitoring Environmental Noise and Carbon Monoxide,” Taiwan Conference on Software Engineering (TCSE), paper 4, July 10-11, 2015, Yunlin, Taiwan.

14.  Chia-Chun Tsai, “Repeater Insertion for 3D Data Bus with TSVs for Reducing Critical Propagation Delay,” International Conference on Computer Science and Information Engineering, pp. 203-208, June 28-29, 2015, Bangkok, Thailand.

15.  Chia-Chun Tsai, Hsin-Long Lee, Je-Wei Chen, and Chi-Bon Hsu “A Breathalyzer Car Safety System,” The Academic Workshop of Changhua-Yunlin-Chiayi Major League University, pp. 39-43, Dec. 12, 2014, Chiayi, Taiwan.

16.  Chia-Chun Tsai, “A Reduced Li-Ion Battery Charger for Portable Applications,” The 9th International Conference on Natural Computation, pp. 1712-1716, July 23-25, 2013, Shengyang, Mainland China.

17.  Trong-Yen Lee, Min-Jea Liu, Chia-Chen Fan, Chia-Chun Tsai, and Haixia Wu, “Low Complexity Digit-serial Multiplier Over GF(2^m) Using Karatsuba Technology,” The 7th International Conference on Complex, Intelligent, and Software Intensive Systems, pp. 461-466, July 3-5, 2013, Taichung, Taiwan.

18.  Chia-Chun Tsai, Che-Ming Yang, Yi-Ru Liu, and Ren-Wei Chung, “First-Aid Hand-rocking Power Generated System,” The 8th International Symposium on Healthcare Information Management, Paper H-04, June 14-15, 2013, Chiayi, Taiwan.

19.  Trong-Yen Lee, Chia-Chen Fan, Min-Jea Liu, and Chia-Chun Tsai, “Embedding Karatsuba Multiplier Technique for Low-Complexity Digit-serial Multiplier GF(2^m),” Conference on Innovative Electronics Design and Applications, pp. 59-64, Dec 21, 2012, Nantou, Taiwan.

20.  Chia-Chun Tsai and Trong-Yen Lee, “Power Awareness for Multi-voltage Island X-Clock Tree Construction with Double-via Insertion,” The 4th Asia Symposium on Quality Electronic Design (ASQED),  pp. 187-192, July 10-11, 2012, Penang, Malaysia.

21.  Chia-Chun Tsai, Tsung-Ming Liu, and Trong-Yen Lee, “Micro Fuel Cell Power Management Circuit Design for Portable Devices,” The 10th International Conference on Fuzzy Systems and Knowledge Discovery, pp. 2506-2509, May 29-31, 2012, Chongqing, Mainland China.

22.  Trong-Yen Lee, Ren-Fu Deng, Chia-Jen Fan, Yan-Hsin Fan, and Chia-Chun Tsai, “A Heuristic Memory Mapping Algorithm for Interface Synthesis,” The 6th Conference on Integrated Opto-Mechatronic Technology and Intellectual Property Rights, Paper No. 1001203, Dec 20, 2011, Taipei, Taiwan.

23.  Chia-Chun Tsai, Chung-Chieh Kuo, and Trong-Yen Lee, “Voltage-Island Aware X-Clock Tree Construction for Power Minimization,” International Conference on Computer Science and Service System, pp. 4132-4135, June 27-29, 2011, Nanjing, Mainland China.

24.  Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Lin-Jeng Gu, and Trong-Yen Lee, “X-Architecture Zero-Skew Clock Tree Construction with Performance and DFM Considerations,” International SOC Design Conference (ISOCC), pp. 294-297, Nov. 22-23, 2010, Incheon, Korea.

25.  Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, and Trong-Yen Lee, “Double-Via Insertion for Improving the Reliability of X-Architecture Clock Tree,” The 21st VLSI Design/CAD Symposium, August 3-6, 2010, Kaohsiung, Taiwan. (Best Paper Nominee)

26.  Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, and Trong-Yen Lee, “Double-via Insertion Enhanced X-Architecture Clock Routing for Reliability,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3413-3416, May 30-June 2, 2010, Paris, France.

27.  Trong-Yen Lee, Shih-Wei Huang, and Chia-Chun Tsai, “Design and Implementation of Remote Laboratory for Reconfiguration System,” Proc. of Intelligent Systems Conference on Engineering Applications, May 2010, Tainan, Taiwan.

28.  Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, and Trong-Yen Lee, “Antenna Violation Avoidance/Fixing for X-Clock Routing,” International Symposium on Quality Electronic Design (ISQED), pp. 508-514, Mar. 22-24, 2010, San Jose, CA, USA.

29.  Trong-Yen Lee, Ting-Chon Wu, and Chia-Chun Tsai, “Design of Adaptive Communication Channel for Network-on-Chip,” The 8^th Conference on Communication Applications, pp. 406-411, Mar. 19, 2010, Taipei, Taiwan.

30.  Trong-Yen Lee, Ming-Wei Lin, and Chia-Chun Tsai, “Predictable Dynamic Virtual Channel Allocation Strategy for Network on Chips,” The 8^th Conference on Communication Applications, Mar. 19, 2010, Taipei, Taiwan.

31.  Trong-Yen Lee, Che-Cheng Hu, and Chia-Chun Tsai, “Adaptive Free Space Management of Online Placement for Reconfigurable Systems,” The International MultiConference of Engineers and Computer Scientists (IMECS), pp. 322-326, Mar 17-19, 2010, Hong Kong.

32.  Trong-Yen Lee, Ku-Yi Cheng, Che-Cheng Hu, and Chia-Chun Tsai, “A New Low Memory Free Space Recording Method for Reconfigurable Systems,” International Conference on High-Speed Circuits Design, pp. H-15-H-19, Oct. 26-27, 2009, Tamsui, Taiwan.

33.  Trong-Yen Lee, Che-Cheng Hu, and Chia-Chun Tsai, “Multi-strategy Online Placement for Dynamically Partial Reconfigurable Device,” International Conference on High-Speed Circuits Design, pp. H-20-H-26, Oct. 26-27, 2009, Tamsui, Taiwan.

34.  Trong-Yen Lee, Shih-Wei Huang, and Chia-Chun Tsai, “Implementation of Real Time Multi-function Apply on Partial Reconfigurable System,” Prof. of  CIA-SP&CD Conference, pp. 85-90, Oct. 2009, Taoyuan, Taiwan.

35.  Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee, Lin-Jeng Gu, and Jan-Ou Wu, “Buffer Insertion and Sizing for X-Architecture Clock Routing,” The 20th VLSI Design/CAD Symposium, August 2009, Hualein, Taiwan.

36.  Chia-Chun Tsai, Chung-Chieh Kuo, and Trong-Yen Lee, “Antenna detection and fixing with jumper insertion for X-clock routing,” in Proceedings of International Ph.D. Student Workshop (IPS), Aug. 2009, Hualein, Taiwan.

37.  Trong-Yen Lee, Chong-Yi Chang, Chang-Ping Hu, and Chia-Chun Tsai, “Hierarchical Genetic-Based HW-SW Partitioning Algorithm for Dynamic Reconfigurable Systems,” The 20th VLSI Design/CAD Symposium, August 2009, Hualein, Taiwan.

38.  Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee, and Jan-Ou Wu, “X-architecture Clock Tree Construction Associated with Buffer Insertion and Sizing,” The 1st Asia Symposium on Quality Electronic Design (ASQED),pp. 298-303, July 15-16, 2009, Kuala Lumpur, Malaysia.

39.  Trong-Yen Lee, Ku-Yi Cheng, Che-Cheng Hu, and Chia-Chun Tsai, “Free Space Managemen for FPGA-based Reconfiguable Systems,” Electronic Technology Symposium, June 19, 2009, Kaohsiung, Taiwan.

40.  Trong-Yen Lee, Ku-Yi Cheng, Che-Cheng Hu, and Chia-Chun Tsai, “Applied Reconfiguable System for LED Display Controller Design,” Electronic Technology Symposium, June 19, 2009, Kaohsiung, Taiwan.

41.  Chia-Chun Tsai, Jing-Wei Hwang, and Guang-Ming Wu, “RFID Applied to Database Management for People In/Out Statistic System,” Information Management and E-Commerce Management Symposium, Paper no. 3, May 30, 2009, Chiayi, Taiwan.

42.  Chia-Chun Tsai, Rei-Ting Xu, and Jian-Chung Chen, “A Music Instrument Platform on Web for Music Classrooms,” Information Management and E-Commerce Management Symposium, Paper no. 17, May 30, 2009, Chiayi, Taiwan.

43.  Chia-Chun Tsai and Jie-Hou You, “X-Architecture Clock Routing with Considering Voltage-Island Placement,” Information Management and E-Commerce Management Symposium, Paper no. 26, May 30, 2009, Chiayi, Taiwan.

44.  Chia-Chun Tsai, Feng-Tzu Hsu, Chung-Chieh Kuo, Jan-Ou Wu, and Trong-Yen Lee, “X-Clock Tree Construction for Antenna Avoidance,” The 9^th International Conference on Solid-State and Integrated-Circuit Technology, Paper H1.6, October 20-23, 2008, Beijing, China.

45.  Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, and Rong-Shue Hsiao, “X-Clock Routing Based on Pattern Matching,” The 21^st Annual IEEE International SOC Conference, pp. 357-360, Sept. 17-20, 2008, Newport Beach, CA, USA.

46.  Chia-Chun Tsai, Feng-Tzu Hsu, Chung-Chieh Kuo, Jan-Ou Wu, and Trong-Yen Lee, “Antenna Effect Consideration for X-Clock Routing,” Proc. The 19th VLSI Design/CAD Symposium, Paper ID:179, Aug. 5-8, 2008, Howard Beach Resort, Kenting, Taiwan.

47.  Trong-Yen Lee, Chang-Ping Hu, and Chia-Chun Tsai, “Hardware-Software Partitioning for Partial Dynamically Self-Reconfigurable Systems,” The 19th VLSI Design/CAD Symposium, Paper ID:059, Aug. 5-8, 2008, Howard Beach Resort, Kenting, Taiwan.

48.  Trong-Yen Lee, Che-Cheng Hu, Yang-Kun Huang, and Chia-Chun Tsai, “A New Approach of Hardware Context-Switch for Dynamic Partial Self-Reconfigurable Systems,” The 19th VLSI Design/CAD Symposium, Paper ID:057, Aug. 5-8, 2008, Howard Beach Resort, Kenting, Taiwan.

49.  Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, and Trong-Yen Lee, “Layer Assignment Considering Manufacturability in X-Architecture Clock Tree,” IEEE 8^th International Conference on Computer and Information Technology (ICCIT), pp. 880-885, July 8-11, 2008, Sydney, Australia.

50.  Chia-Chun Tsai, Chia-Yi Chang, Wei-Bin Chang, and Guang-Ming Wu, “The Delay Effects Considering Vias in X-Clock Routing,” The 16^th National Conference on Automation Technology, pp. 1184-1188, June 27-28, 2008, Kaoshiung, Taiwan.

51.  Trong-Yen Lee, Yan-Hsin Fan, Chia-Chun Tsai, and Rong-Shue Hsiao, “Sophisticated Computation of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems,” Proceedings of IEEE International Conference on Innovative Computing, Information and Control, June 18-20, 2008, Dalian, China.

52.  Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, Chia-Chun Tsai, and Rong-Shue Hsiao, “Hardware Context Switching Methodology for Dynamically Partially Reconfigurable Systems,” National Computer Symposium (NCS), Vol. 2, pp. 195-199, December 20-21, 2007, Taichung, Taiwan.

53.  Trong-Yen Lee, Chou-Chuan Yao, Yang-Hsin Fan, Chia-Chun Tsai, and Rong-Shue Hsiao, “Design of Automatic Timing Verification Tool for FPGA Systems,” National Computer Symposium (NCS 2007), Vol. 2, pp. 300-310, December 20-21, 2007, Taichung, Taiwan.

54.  Trong-Yen Lee, Yan-Hsin Fan, Yu-min Cheng, Chia-Chun Tsai, and Rong-Shue Hsiao, “Enhancement of Hardware-software Partition for Embedded Multiprocessor FPGA Systems,” IEEE International Conference on Intelligent Information Hiding and Multimedia Signal Processing, Vol. 1, pp. 19-22, November 26-28, 2007, Kaohsiung, Taiwan.

55.  Chia-Chun Tsai, Kwok-Fong Kual, Trong-Yen Lee, and Rong-Shue Hsiao, “A Transmission Interface Integrated Circuit Design for ISO14443A RFID Transponders,” International SoC Design Conference (ISOCC), pp. 509-512, Oct. 15-16, 2007, Seoul, Korea.

56.  Trong-Yen Lee, Chieh-I Yu, Yan-Hsin Fan, Chia-Chun Tsai, and Rong-Shue Hsiao, “An Efficient Task Scheduling Algorithm for Partial Reconfigurable FPGA-Based Systems,” The Conference on Innovative Applications of System Prototyping and Circuits Design, Paper ID: P09, September 28, 2007, Tainan, Taiwan.

57.  Trong-Yen Lee, Chang-Ping Hu, Yang-Kun Huang, Chia-Chun Tsai, and Rong-Shue Hsiao, “MPEG-2 Video Decoder System Analysis and Hardware-Software Partition,” The Conference on Innovative Applications of System Prototyping and Circuits Design, Paper ID: P72, September 28, 2007, Tainan, Taiwan.

58.  Trong-Yen Lee, Yan-Hsin Fan, Shih-Chin Yen, Chia-Chun Tsai, and Rong-Shue Hsiao, “An Integrated Functional Verification Tool for FPGA Systems,” IEEE International Conference on Innovative Computing, Information and Control, September 5-7, 2007, Kumamoto Japan.

59.  Trong-Yen Lee, Yan-Hsin Fan, Yu-min Cheng, Chia-Chun Tsai, and Rong-Shue Hsiao, “Hardware-oriented Partition for Embedded Multiprocessor FPGA Systems,” IEEE International Conference on Innovative Computing, Information and Control, September 5-7, 2007, Kumamoto, Japan.

60.  Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, and Rong-Shue Hsiao, “A Topology-Based Construction for X-Architecture Clock Routing,” The 18th VLSI Design/CAD Symposium, pp. 166-169, August 2007, Hualein, Taiwan.

61.  Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, and Rong-Shue Hsiao, “An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA System,” International Multiconference of Engineers and Computer Scientists (IMECS), pp. 346-351, March 21-23, 2007, Hong Kong.

62.  Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Hsieh, Trong-Yen Lee, and Rong-Shue Hsiao, “RLC Clock Tree Construction Based on DME Algorithms Associated with Grey Relational Cluster,” IEEE The Fourth International Conference on Information Technology and Applications (ICITA), pp. 706-711, Jan 15-18, 2007, Harbin, China.

63.  Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, and Rong-Shue Hsiao, “Delay Modeling for RLC Trees with LU Decomposition Matrice,” IEEE The Fourth International Conference on Information Technology and Applications (ICITA), pp. 688-692, Jan 15-18, 2007, Harbin, China.

64.  Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, and Trong-Yen Lee, “Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction,” IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), pp. 813-816, Dec. 4-7, 2006, Singapore.

65.  Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, and Rong-Shue Hsiao, “Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion,” IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), pp. 1287-1290, Dec. 4-7, 2006, Singapore.

66.  Trong-Yen Lee, Che-Cheng Hu, Yung-Lin Hsu, Chia-Chun Tsai, and Rong-Shue Hsiao, ”A Low Cost GPS Satellite Signal Baseband System Using FPGA Prototyping,” International Computer Symposium (ICS), Paer ID: #43, Dec. 4-6, 2006, Taiwan.

67.  Trong-Yen Lee, Jian Guo, Che-Cheng Hu, Chia-Chun Tsai, and Rong-Shue Hsiao, “Design of Digital RF Power Control for GPS Satellite Signal Emulator” The Workshop on Consumer Electronics and Signal Processing, Paper ID: E0X0020, 16 Nov., 2006, Hsin-Chu, Taiwan.

68.  Kuang-Hung Chiang and Chia-Chun Tsai, “A Low-Cost Approach for Security and Privacy of RFID Application System,” International Conference on Information Technology and Integration of Manufacturing and Business (ITIMB), pp. 385-392, Oct. 28, 2006, Taiwan.

69.  Trong-Yen Lee, Yang-Hsin Fan, and Chia-Chun Tsai, “Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion,” International Conference on Innovative Computing, Information and Control, Aug. 30-Sept. 1, 2006, Beijing.

70.  Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, and Rong-Shue Hsiao, “Delay Modeling Based on Second-Order Moment Matching for RLC Trees,” The 17th VLSI Design/CAD Symposium, Paper ID:182, August 2006, Hualein, Taiwan.

71.  Jan-Ou Wu, Chia-Chun Tsai, Yu-Ting Hsieh, Chung-Chieh Kuo, and Trong-Yen Lee, “Exact Zero-Skew RLC Clock Tree Construction Based on Tapping Point Numerical Search,” The 17th VLSI Design/CAD Symposium, Paper ID:140, August 2006, Hualein, Taiwan.

72.  Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, Chia-Chun Tsai, and Rong-Shue Hsiao, “A FPGA-Based Digital Baseband System for GPS Simulator,” International PhD Student Workshop on SOC, July 24-28, 2006, Taipei, Taiwan.

73.  Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, and Rong-Shue Hsiao, “A Single Chip Image Sensor Embedded Smooth Spatial Filter with A/D Conversion,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 425-428, May 21-24, 2006, Island of Kos, Greece.

74.  Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, and Rong-Shue Hsiao, “Coupling Aware RLC-Based Clock Routings for Crosstalk Minimization,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 497-500, May 21-24, 2006, Island of Kos, Greece.

75.  Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, and Chia-Chun Tsai, “Inductance Extraction for General Interconnect Structures,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4647-4650, May 21-24, 2006, Island of Kos, Greece.

76.  Trong-Yen Lee, Yung-Lin Hsu, Che-Cheng Hu, Chia-Chun Tsai, and Rong-Shue Hsiao, “The Design and Implementation of Multi-channel GPS Emulator,” The 4th Conference on Communication Applications, pp. 61-66, March 17, 2006, Taipei, Taiwan.

77.  Trong-Yen Lee, Hong-Lin Hsing, Che-Cheng Hu, Chia-Chun Tsai, and Rong-Shue Hsiao, “The Implementation of Satellite Signal Generation and User Interface for GPS Emulator,” The 4th Conference on Communication Applications, pp. 242-246, March 17, 2006, Taipei, Taiwan.

78.  Trong-Yen Lee, Li-Wen Lai, Che-Cheng Hu, Chia-Chun Tsai, and Rong-Shue Hsiao, “The implementation of Digital-Based Signal Generation for GPS Emulator,” The 4th Conference on Communication Applications, pp. 182-187, March 17, 2006, Taipei, Taiwan.

79.  Pei-Yung Hsiao, Chia-Hao Lee, and Chia-Chun Tsai, “A Novel CMOS Imager With 2-Dimensional Binarization and Edge Detection for Highly Integrated Imaging Systems,” IEEE International Conference on Consumer Electronics, Paper ID:1347, pp. 71-72,  Jan. 7-11, 2006, Las Vegas, USA.

80.  Wen-Ta Lee, Ming-Chang Lee, Chien-Liang Yeh, Yuh-Shyan Hwang, Chia-Chun Tsai, and Trong-Yen Lee, “A New Efficient Normalization VLSI Architecture for MAP Decoder,” International  Symposium on  Communications, Paper ID:142, Nov. 20-22, 2005, NSYSU, Taiwan.

81.  Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, and Rong-Shue Hsiao, “A Low Power Design Method for CMOS Flash ADC,” Workshop on Consumer Electronics and Signal Processing (WCE), Paper ID:127, Nov. 17-18, 2005, NYUST, Taiwan.

82.  Trong-Yen Lee, Shih-Chin Yen, Yang-Hsin Fan, Chia-Chun Tsai, and Rong-Shue Hsiao, “VERR: The Design of FPGA System Verification Tool,” The Workshop on Consumer Electronics and Signal Processing (WCE), Paper ID:152, Nov. 17-18, 2005, NYUST, Taiwan.

83.  Chia-Chun Tsai, Kai-Min Wang, Trong-Yen Lee, and Rong-Shue Hsiao, “Three-stage Linear Li-Ion Battery Charger,” Workshop on Consumer Electronics and Signal Processing (WCE), Paper ID:238, Nov. 17-18, 2005, NYUST, Taiwan.

84.  Kwok-Fong Kual, Chia-Chun Tsai, and Trong-Yen Lee, “A Survey of Passive 13.56MHz RFID Transponder Circuit Design,” The Workshop on Consumer Electronics and Signal Processing (WCE), Paper ID:328, Nov. 17-18, 2005, NYUST, Taiwan.

85.  Wei-Ting Yen, Pei-Yung Hsiao, Szi-Wen Chen, and Chia-Chun Tsai, “The Design of Multi-Lamp Driving System for Cold Cathode Fluorescent Lamp,” The Workshop on Consumer Electronics and Signal Processing (WCE), Paper ID:336, Nov. 17-18, 2005, NYUST, Taiwan.

86.  Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao, and Pei-Yung Hsiao, “A Current-Mode CMOS Image Sensor Based on Smooth Spatial Filter,” International SoC Design Conference, pp. 83-86, Oct. 20-21, 2005, Seoul, Korea.

87.  Chia-Chun Tsai, Chien-Wen Kao, Jan-Ou Wu, Trong-Yen Lee, and Rong-Shue Hsiao, “Crosstalk Analysis and Reduction for RLS-Based Clock Routings,” The 16th VLSI Design/CAD Symposium, Paper ID:77, August 2005, Hualein, Taiwan.

88.  Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, and Rong-Shue Hsiao, “Zero-Skew Driven for Buffered RLC Clock Tree Construction,” Proc. The 16th VLSI Design/CAD Symposium, Paper ID:128, August 2005, Hualein, Taiwan.

89.  Trong-Yen Lee, Jen-Pu Tseng, Yang-Hsin Fan, Chia-Chun Tsai, and Rong-Shue Hsiao, “Design of a Hardware-Software Partitioning Tool for FPGA Systems,” The 16th VLSI Design/CAD Symposium, Paper ID:189, August 2005, Hualein, Taiwan.

90.  Trong-Yen Lee, Yang-Hsin Fan, Shih-Chin Yen, Chia-Chun Tsai, and Rong-Shue Hsiao, “VERR: Design a Verification Tool for FPGA Systems,” Proc. The 16th VLSI Design/CAD Symposium, Paper ID:190, August 2005, Hualein, Taiwan.

91.  Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, and Wen-Ta Lee, “Zero-Skew Driven for RLC Clock Tree Construction in SoC,” The Third International Conference on Information Technology and Applications (ICITA), Vol. 1, pp. 561-566 (#370), July 4-7 2005.

92.  Trong-Yen Lee, Yu-Min Cheng, Yang-Hsin Fan, Chia-Chun Tsai, and Rong-Shue Hsiao, "A HW-SW Partitioning for Multiprocessor Embedded Systems,” International Conference of Information Management (ICIM), paper no. ITA-461-P, May 28, 2005, Taipei Taiwan. (In Chinese)

93.  Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, and Jiann-Jong Chen, "A New CCII-Based Pipelined Analog to Digital Converter," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 6170-6173, May 23-26, 2005, Kobe, Japan.

94.  Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, and Yuh-Shyan Hwang, “A New Low-power Turbo Decoder Using HDA-DHDD Stopping Iteration,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1040-1043, May 23-26, 2005, Kobe, Japan.

95.  Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee and Yuh-Shyan Hwang, “A New VLSI Architecture for Low-Memory Cost  SISO Decoder,” The IEEE International Conference on Systems and Signals (ICSS), pp. 1314-1318, April 28-29, 2005, Kaohsiung, Taiwan.

96.  Wen-Ta Lee, Ying-Chung Liu, Chia-Chun Tsai, Trong-Yen Lee, and Yuh-Shyan Hwang, “A New Low Cost VLSI Architecture for Quantized Two Steps Search Algorithm of Motion Estimation,” The IEEE International Conference on Systems and Signals (ICSS), pp. 409-413, April 28-29, 2005, Kaohsiung, Taiwan.

97.  Trong-Yen Lee, Jen-Pu Tseng, Yang-Hsin Fan, Chia-Chun Tsai, Wen-Ta Lee and Yuh-Shyan Hwang, “Hardware-Software Partitioning Tool Using Multiple Algorithms for FPGA Systems,” The IEEE International Conference on Systems and Signals (ICSS), pp. 537-542, April 28-29, 2005, Kauhsiung Taiwan.

98.  Trong-Yen Lee, Yang-Hsin Fan, Yu-Ming Cheng and Chia-Chun Tsai, "A Hardware-Software Partitioning for Multiprocessor Embedded Systems," The IEEE International Conference on Systems and Signals (ICSS), pp. 543-548, April 28-29, 2005, Kauhsiung Taiwan.

99.  Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, and Yuh-Shyan Hwang, "A Retargetable Code Generation Methodology for Embedded Systems," The International Computer Symposium (ICS), pp. 765-770, Dec. 15-17, 2004, Taipei, Taiwan.

100. Trong-Yen Lee, Chi-Hsiung Dai, Yang-Hsin Fan, Chia-Chun Tsai, Wen-Ta Lee, and Yuh-Shyan Hwang, "a Hardware-software partitioning for reconfigurable DSP-based SoC," The 1st Applied Science and Technology Conference (ATSC),  paper no. QK04, Dec. 09-10, 2004, Kauhsiung Taiwan.

101. Chia-Chun Tsai, Chin-Yen Lin, Yuh-Shyan Hwang, Wen-Ta Lee and Trong-Yen Lee, “A Multi-Mode LDO-Based Li-Ion Battery Charger in 0.35μm CMOS Technology,” IEEE Asia-Pacific Conference on Circuits and Systems, pp. 49-52, Dec. 6-9, 2004, Tainan, Taiwan.

102. Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, and Yuh-Shyan Hwang, “New SISO Decoder Chip Design,” National Symposium on Telecommunications (NST), DSP-2-5, Dec. 3-4, 2004, Kinglong, Taiwan.

103. Trong-Yen Lee, Cheng-Fu Huang, Chia-Chun Tsai, Wen-Ta Lee, and Yuh-Shyan Hwang, "SoC test scheduling using simulated annealing algorithm," Proceeding of Operational Research (ORTM) 2004, Nov. 12, 2004, Taipei, Taiwan.

104. Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, and Yuh-Shyan Hwang, “RCGES: Retargetable Code Generation for Embedded Systems,” The 2rd International Symposium on Automated Technology for Verification and Analysis (ATVA), Oct. 31-Nov. 3, Taipei, Taiwan, pp. 415-425, 2004.

105. Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee and Trong-Yen Lee, “New CCII-Based Sample-and-Hold and MDAC Circuits for Pipelined ADC,” The 15th VLSI Design/CAD Symposium, B4-5, August 2004, Taiwan.

106. Trong-Yen Lee, Chen-Fu Huang, Chia-Chun Tsai, Wen-Ta Lee and Yuh-Shyan Hwang, “SOC Test Scheduling Using Simulated Annealing Algorithm,” The 15th VLSI Design/CAD Symposium, P3-5, August 2004, Taiwan.

107. Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Wen-Ta Lee and Trong-Yen Lee, “Minimum Skew Upward Propagation in RLC Clock Tree,” The 15th VLSI Design/CAD Symposium, P3-9, August 2004, Taiwan.

108. Chia-Chun Tsai, Kai-Wei Hong, Yuh-Shyan Hwang, Wen-Ta Lee, and Trong-Yen Lee, “New Power Saving Design Method for CMOS Flash ADC,” The IEEE 47^th International Midwest Symposium on Circuits and Systems (MWSCAS 2004, Hiroshima Japan), pp. III-371-III-374, July 2004.

109. Chia-Chun Tsai, Sheng-Bin Dai, Wen-Ta Lee, and Trong-Yen Lee, “The RF Circuit Design for Magnetic Power and Data Transmission,” The 2^nd International Conference on Information Technology and Applications (ICITA 2004), Paper 56-5, pp. 280-283, Jan. 2004.

110. Chia-Chun Tsai, Po-Kuan Tien, and Wen-Ta Lee, “Chip Implementation for Power and Data Wireless Transfer,” International Conference on Informatics, Cybernetics and Systems (ICICS), pp. 1319-1325 (Paper 10910), Dec. 2003, Taiwan.

111. Chia-Chun Tsai, Jan-Ou Wu, Yen-Chun Lu, Wen-Ta Lee, and Trong-Yen Lee, "Clock Methodology Based on Grey Relation Clustering," International Conference on Informatics, Cybernetics and Systems (ICICS), pp. 1313-1318 (Paper 10909), Dec. 2003, Taiwan.

112. Trong-Yen Lee, Pou-An Hsiung, I-Mu Wu, Chia-Chun Tsai, and Wen-Ta Lee, “The Design of Synthesis Tool for Interrupt-based Embedded Software,” International Conference on Informatics, Cybernetics, and Systems (ICICS), pp. 1284-1289 (Paper 10405), Dec. 2003, Taiwan.

113. Chia-Chun Tsai, Sheng-Bin Dai, Wen-Ta Lee, and Trong-Yen Lee, “The RF Circuit Design for ISO/IEC 14443-2 Type B Contactless Transmission,” International Symposium on Communications (ISCOM), Paper 122, Dec. 2003, Taiwan.

114. Wen-Ta Lee, Geng-Huan Lin, Chia-Chun Tsai, and Trong-Yen Lee, “A Window Based Viterbi Decoder IP Builder for RCPC Codes,” International Symposium on Communications (ISCOM), Paper 123, Dec. 2003, Taiwan.

115. Wen-Ta Lee, Ping-Hung Liu, Pei-Yung Hsiao, and Chia-Chun Tsai, “With Data Interlacing Reuse on Low Hardware Resource VLSI Design of Motion Estimation,” International Symposium on Communications (ISCOM), Paper 116, Dec. 2003, Taiwan.

116. Wen-Ta Lee, Chien-Fang Pang, Chia-Chun Tsai, and Trong-Yen Lee, “Reconfigurable Punctured Encoder/Decoder IP Generator,” The Workshop on Consumer Electronics (WCE), Paper e0020, Nov. 27-28. 2003, Taiwan.

117. Wen-Ta Lee, Kai-Yun Zheng, Chia-Chun Tsai, and Trong-Yen Lee, “Chip Implementation for CD-ROM Spindle Motor Driver,” The Workshop on Consumer Electronics (WCE), Paper d0015, Nov. 27-28. 2003, Taiwan.

118. Chia-Chun Tsai, Po-Kuan Tien, Sheng-Bin Dai, Jan-Ou Wu, and Wen-Ta Lee, “Power and Data Transfer Techniques Apply for RFID System,” Taiwan EMC Conference, pp. 347-350, October 2003, Taiwan.

119. Chia-Chun Tsai, Sheng-Bin Dai, King-Yen Lin, Wen-Ta Lee, and Trong-Yen Lee, “Antenna Design for Wireless Magnetic Coupling System,” Taiwan EMC Conference, pp. 642-646, October 2003, Taiwan.   

120. Chia-Chun Tsai, Hsu-Heng Wu, and Wen-Ta Lee, “A Fractional Frequency Synthesizer Based on ADPLL,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), pp. 151-154, October 2003, Taiwan.

121. Trong-Yen Lee, I-M Wu, Pou-An Hsiung, C-P Chang, Chia-Chun Tsai, and Wen-Ta Lee, "Design of a Software Tool for Real-Time Embedded Systems," The 14th Workshop on Object-Orient Technology and Applications (OOTA), pp. 609-616, Sept. 12, 2003, Taiwan.

122. Wen-Ta Lee, Hung-Ying Chen, Pei-Yung Hsiao, and Chia-Chun Tsai, “An Efficient Lifting Based Architecture For 2-D DWT Used In JPEG-2000,” The 14th VLSI Design/CAD Symposium, paper P4-9, pp. 577-580, August 2003, Taiwan.

123. Wen-Ta Lee, Geng-Huan Lin, Chia-Chun Tsai, and Trong-Yen Lee, “A Viterbi Decoder IP Builder for Punctured Convolutional Code,” The 14th VLSI Design/CAD Symposium, paper P3-10, pp. 417-420, August 2003, Taiwan.

124. Pei-Yung Hsiao, Yu-Chun Hsu, Wen-Ta Lee, and Chia-Chun Tsai, “An Analog Design of Spatial Filter Embedded in the CMOS Image Sensor,” The 14th VLSI Design/CAD Symposium, paper P2-6, pp. 261-264, August 2003, Taiwan.

125. Wen-Ta Lee, Cherng-En Yeh, and Chia-Chun Tsai, “A Retargetable Viterbi Decoder IP Generator,” National Symposium on Telecommunication, paper C-39, Dec. 2002, Taiwan.

126. Wen-Ta Lee, Wen-Sheng Chiang, and Chia-Chun Tsai, “A Reversible VLSI Architecture for Analysis and Synthesis of Discrete Wavelet Transform,” The 13th VLSI Design/CAD Symposium, paper P-32, August 2002, Taiwan.

127. Wen-Ta Lee, Ping-Hung Liu, Pei-Yung Hsiao, and Chia-Chun Tsai, “A Novel High-Performance VLSI Architecture for Motion Estimation Using Data Access Exchange,” The 13th VLSI Design/CAD Symposium, paper P-31, August 2002, Taiwan.

128. Wen-Hua Luo, Wen-Ta Lee, and Chia-Chun Tsai, “IC Design of a Burst-Error-Correcting Viterbi Decoder,” The Workshop on Consumer Electronics, Oct. 2001, Taiwan.

129. Chien-Hung Lai, Chia-Chun Tsai, and Wen-Ta Lee, “A 10-Bit Switched-Current Digital to Analog Converter,” The 12th VLSI Design/CAD Symposium, paper A1-8, August 2001, Taiwan.

130. Chih-Ching Yan, Chia-Chun Tsai, and Wen-Ta Lee, “Performance Driven Based on Signal Repeater Insertion for RLC Interconnections,” The 12th VLSI Design/CAD Symposium, paper B1-9, August 2001, Taiwan.

131. Shuenn-Shi Chen, Jong-Jang Chen, Chia-Chun Tsai, and Sao-Jie Chen, “An Even Wiring Approach to the Ball Grid Array Package Routing,” International Conference on Computer Design, pp. 303-306, Oct. 1999.

132. Yu-Wen Chu and Chia-Chun Tsai, “Community Safety System Implementation with CPLD Techniques,” The 14th National Technical and Vocational Symposium, pp. 57-66, May 1999.  

133. Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, and Chia-Chun Tsai, "An Automatic Router for the Pin Grid Array Package,” ASP-DAC’99, pp. 133-136, Jan. 1999, Hong Kong.

134. Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, and Jan-Ming Ho, "An Efficient Two-Level Partitioning Algorithm for VLSI Circuits,” ASP-DAC’99, pp. 69-72, Jan. 1999, Hong Kong.

135. Chia-Chun Tsai, Zen-hwang Wang, and Wen-Cheng Chang, “Stick Controller Implementation with FPGA for Computer Games,” The 13th National Technical and Vocational Symposium, pp. 307-317, May 1998.  

136. Chia-Chun Tsai, Yuh-Ge Chain, and Swu-Hwa Kuo, “Bus Repeater Implementation,” The 13th National Technical and Vocational Symposium, pp. 297-306, May 1998.  

137. Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, and Chia-Chun Tsai, "A Matching Approach to Segmented Channel Routing,” The 8th VLSI Design/CAD Symposium, pp. 273-276, August 1997, Taiwan.

138. H. Y. Hsu, Sao-Jie Chen, and Chia-Chun Tsai, "An Approach to One-Dimensional Compaction,” The 8th VLSI Design/CAD Symposium, pp. 269-272, August 1997, Taiwan.

139. C. A. Hsieh, C. Yu, Chia-Chun Tsai, and Sao-Jie Chen, "Design and Implementation of a Multicast Header Translator for ATM System,” The 8th VLSI Design/CAD Symposium, pp. 157-160, August 1997, Taiwan.

140. Chia-Chun Tsai, “Hybrid Routing Techniques for Applications to Multi-Chip Modules,” The 16^th Engineering Technical Communication, pp. 41-44, May 1996.

141.    Chia-Chun Tsai, “VLSI Physical Design Automation Techniques,” The Electronic Month Issue, Vol. 2, No. 2, pp. 87-95, February 1996.  

142. Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, and Ting-Ting Lin, "Performance Driven Multiple-Source Bus Synthesis Using Buffer Insertion,” ASP-DAC’95, CHDL’95, and VLSI’95, pp. 273-278, August 1995, Japan.

143. De-Yu Kao, Chia-Chun Tsai, Chung-Kuan Cheng, and Ting-Ting Lin, "New Design and Implementation for Signal Repeaters,” The Sixth VLSI Design/CAD Workshop, pp. 173-176, August 1995, Taiwan.

144. Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, and Chia-Chun Tsai, "One-Phase Technology Mapping for EPGSs Using Extended GBDD Hash Tables,” International Symposium on VLSI Technology, Systems and Applications (VLSI), pp. 73-78, May 1995, Taiwan.

145. Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, and Jan-Ming Ho, "An Efficient Approach for Via Minimization in Multi-Layer VLSI/PCB Routing,” Custom Integrated Circuit Conference (CICC), pp. 473-476, May 1995, USA.

146. Chwan-Ming Wang, Chia-Chun Tsai, and Sao-Jie Chen, "A Routing System for the PGA Package,” The Fifth VLSI Design/CAD Workshop, pp. 362-367, August 1994, Taiwan.

147. Chia-Chun Tsai, and Sao-Jie Chen, "An Algorithm for Routing a PGA Package,” The Fourth VLSI/CAD Workshop, pp. 30-34, August 1993, Taiwan.

148. Chia-Chun Tsai, and Sao-Jie Chen, "Planar Routing on a Pin Grid Array Package,” The Third International Conference on Computer Aided Design and Computer Graph, pp. 439-444, August 1993, Mainland China.

149. Chia-Chun Tsai, Shuenn-Shi Chen, and Pei-Yung Hsiao, "A practical router for VLSI circuit design,” The Third International Conference of Young Computer Scientists, pp. 4.52-4.56, July 1993, Mainland China.

150. Ming-Fu Shiao, Chieh Changfan, Sao-Jie Chen, and Chia-Chun Tsai, "An Efficient Signal Redistribution Algorithm for Multichip Module,” Custom Integrated Circuit Conference (CICC), pp. 29.6.1-29.6.4, May 1993, USA.

151. Chia-Chun Tsai, and Sao-Jie Chen, "Planar Moat Routing,” The Third VLSI/CAD Workshop, pp. 169-178, March 1992, Taiwan.

152. Chia-Chun Tsai, Sao-Jie Chen, Yuh-Lin Chen, and Yu-Hen Hu, "Planning Strategies for Area Routing,” The European Conference on Design Automation (EDAC), pp. 338-342, March 1992, Belgium.

153. Pei-Yung Hsiao, Chiao-Yi Lin, and Chia-Chun Tsai, "Minimum Partition for the Space Region of VLSI Layout,” The Fifth International Conference on VLSI Design, pp. 273-276, January 1992, India.

154. Yuh-Lin Chen, Sao-Jie Chen, Chia-Chun Tsai, and Yu-Hen Hu, "GEAR: A General Area Router Using Planning Approach,” International Symposium on VLSI Technology, Systems and Applications (VLSI) , pp. 182-186, May 1991, Taiwan.

155. Chia-Chun Tsai, Sao-Jie Chen, Pei-Yung Hsaio, and Wu-Shiung Feng, "Hybrid Routing on Multichip Modules,” Custom Integrated Circuit Conference (CICC), pp. 28.4.1-28.4.4, May 1991, USA.

156. Pei-Yung Hsiao and Chia-Chun Tsai, "A New Plane-Sweep Algorithm Based on Spatial Data Structure for Overlapped Rectangles in 2-D plane,” IEEE Computer Software & Applications Conference (COMPSAC), pp. 347-352, October 1990, USA.

157. Pei-Yung Hsiao, K. H. Li, and Chia-Chun Tsai, "A Sweeping Line Algorithm Based on Two Dimensional Region Search,” IEEE Region 10 Conference on Computer and Communication Systems (TENCON), pp. 496-500, September 1990, Hong Kong.

158. Chia-Chun Tsai, Sao-Jie Chen, and Wu-Shiung Feng, "An Alternating Router for Compacted Routing Area,” The Second VLSI/CAD Workshop, March 1990, Taiwan.

159. Chia-Chun Tsai, Sao-Jie Chen, and Wu-Shiung Feng, "An H-V Tile-Expansion Router,” National Computer Symposium (NCS), pp. 106-115, December 1989, Taiwan.

160. Chia-Chun Tsai, Wu-Shiung Feng, Sao-Jie Chen, Pei-Yung Hsiao, and Hsiao-Fong Chen, "Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme,” Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC), pp. 173-178, June 1989, Japan.

161. Pei-Yung Hsiao, Hsiao-Fong. Chen, Wu-Shiung Feng, Sao-Jie Chen, and Chia-Chun Tsai, "An Improved Control Strategy For Expert Layout Compaction Design,” The International Association of Science and Technology for Development (IASTED), pp. 220-223, June 1989, Switzerland.

162. Chia-Chun Tsai, and Wu-Shiung Feng, "HILAS¾Hierarchical and Interactive Layout System,” Electron Devices and Materials Symposium (EDMS), pp. 303-308, July 1987, Taiwan.

163. Chia-Chun Tsai, S. T. Kuo, T. C. Uang, Lin-Jeng Wang, Ko-Hu Yeap, and Wu-Shiung Feng, "Hierarchical Layout System,” International Symposium on VLSI Technology, Systems and Applications (VLSI), pp. 292-296, May 1987, Taiwan.

164. Shuenn-Shiung Jan, Chia-Chun Tsai, and Wu-Shiung Feng, "LED--A Net-List Driven Layout Editor,” Electron Devices and Materials Symposium (EDMS), pp. 39-44, July 1986, Taiwan.

Books:

1.       Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai and Rong-Shue Hsiao, Chapter Title: Partitioning Strategy for Embedded Multiprocessor FPGA Systems, in Book Title: Trends in Intelligent Systems and Computer Engineering, ISBN: 978-0-387-74934-1, International Association of Engineers, 2008.

2.        Chia-Chun Tsai, “Electronic Engineering Lecture 1~10,” Chung-Hwa Correspondence School, Overseas Chinese Affairs Commission, October 2002, Taiwan, ROC. 

3.        Chia-Chun Tsai, “VLSI Design Using Tanner Tool,” MOE Text-Material 35, July 1998.

4.        Chia-Chun Tsai, “VLSI Introduction,” MOE Text-Material 23, June 1997.

5.        Wen-Ta Lee and Chia-Chun Tsai, “VLSI Design Experiments,” MOE Text-Material, June 1995.

6.        Chia-Chun Tsai and Wen-Ta Lee, “IC Chip Design,” MOE Text-Material, June 1994.

7.        Chia-Chun Tsai, “An Integrated Approach to Block Placement, Routing, and Compaction in VLSI Circuit Layout,” Ph.D. Dissertation, Graduate Institute of Electrical Engineering, Natinal Taiwan University, October 1991.   (Advisors: Profs. Sao-Jie Chen and Wu-Shiung Feng)

8.        Chia-Chun Tsai and Wu-Shiung Feng, “HILAS: Hierarchical and Interactive LAyout System,” Master Thesis, Graduate Institute of Electrical Engineering, National Taiwan University, July 1987.   (Advisor: Prof. Wu-Shiung Feng)

9.        Chia-Chun Tsai, “Digital Electronic Experiments and Applications,” Microport Computer Company, August 1986, Taiwan, ROC. 

10.    Chia-Chun Tsai, “Industrial Electronic Experiments and Applications,” Published No. 31299, Microport Computer Company, Initial version in 1983, Revised version in 1987, Taiwan, ROC. 

11.    Chia-Chun Tsai, “Practical Electronic Circuit Experiments (I & II),” Microport Computer Company, October 1979, Taiwan, ROC. 

Others:

1.          蔡加春，“永懷小學恩師--- 趙錦堂老師”，國立臺北科技大學校訊，Dec. 1, 1998.

2.          蔡加春，“國立臺北技術學院 電子工程系四技與二技課程草案介紹”，國立臺北工專電子工程學刊，pp. 135-142，April 1994.

3.          蔡加春，“超大型積體電路實體設計面面觀”，國立臺北工專電子工程學刊，pp. 42-54，April 1993.

4.          蔡加春，“參加第二十八屆國際技能競賽觀後感”，南港工職青年第十二期，pp. 18-23，December 1985.